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1/28 features 4.5v to 14v wide input supply voltage range built-in mosfet and synchronous rectifier i 2 c programmable supplies output voltage (0.8 to 6v) power on sequence soft-start timing switching frequency (300khz to 2.2mhz) individual current limit optional power saving mode at light loads non volatile memory (nvm) with up to 10,000 times write operation 0.8v, high accuracy reference (1%) current-mode control with simple compensation circuit external synchronization power good protection thermal shutdown overvoltage transient protection overcurrent protection 32-pin 4mm x 4mm tqfn package applications fpga and dsp supplies video processor supplies applications processor power description the xr77103 features three synchronous wide input range high efficiency buck converters. each converter is digitally programmable requiring minimal external components thus providing the smallest size solution possible. the converters can operate in 5v, 9v, and 12v systems and have integrated power switches. the output voltage of each converter can be adjusted by programming the values in the v out setting registers through i 2 c interface. the adjustable range is 0.8 to 6v with 50mv resolution. the output voltage also can be set externally using an external resistor divider. output sequence among the outputs, soft-start time and the peak inductor current limit are also set through i 2 c. the switching frequency of the converters can either be set with i 2 c or can be synchronized to an external clock connected to sync pin if needed. the switching regulators are designed to operate from 300khz to 2.2mhz. each converter operates in phase or out-of-phase according to the value in the phase setting register. this can minimize the input filter requirements. xr77103 features a supervisor circuit that monitors each converter output. pgood pin is asserted once sequencing is done, all outputs are reported in regulation, and the reset timer expires. the polarity of the signal is active high. xr77103 also features a light load pulse skipping mode (psm). it is set through i 2 c. the psm mode allows for a reduction on the input power supplied to the system when the host processor is in stand-by (low activity) mode. universal pmic 3-output programmable buck regulator xr 77103 rev1b
2/28 typical application figure 1. typical application xr77103 v in = 5.5 to 14v v out3 = 0.8 to 6v 25 26 osc pgood internal supply 31 15 10 6 24 27 19 5 ep vin3 vin2 vin1 vcc pgood gnd dgnd agnd en sync buck1 9 12 11 8 7 buck2 16 14 13 17 18 buck3 32 30 29 1 2 comp3 vout3 lx3 bst3 28 4 vin vin pgood v out1 = 0.8 to 6v v out2 = 0.8 to 6v lx3 comp1 vout1 lx1 bst1 lx1 comp2 vout2 lx2 bst2 lx2 i 2 c interface 22 scl 21 sda nvm 23 vl 20 nwr 3.3v a0 3 xr 77103 rev1b
3/28 absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. v in1 , v in2 , v in3 , lx1, lx2, lx3 ....................... -0.3v to 18v vl, en, scl, sda, nwr, a0, v cc .................... -0.3v to 7v pgood, sync ................................................. -0.3v to 7v bst# to lx# ...................................................... -0.3v to 7v agnd, dgnd to gnd .................................... -0.3v to 0.3v storage temperature .................................... -65c to 150c junction temperature ................................................. 150c power dissipation ..................................... internally limited lead temperature (soldering, 10 seconds) ................ 260c cdm ............................................................................ 700v esd rating (hbm C human body model) ....................... 2kv operating conditions v in ..................................................................... 4.5v to 14v v cc ................................................................... 4.5v to 5.5v lx# ................................................................ -0.3v to 14v (1) junction temperature range (t j ) .................. -40c to 125c xr77103 package power dissipation max at 25c ..... 3.4w xr77103 thermal resistance ja ............................. 30c/w note: 1. lx# pins dc range is from -0.3v, transient -1v for less than 10ns. electrical characteristics t a = 25c, v in = 12v, en = v cc , f sw = 1mhz, unless otherwise specified. limits applying over the full operating temperature range are denoted by a ?. symbol parameter conditions ? min typ max units power supply characteristics v in input voltage range ? 5.5 14 v v in input voltage range vcc tied to vin for v in = 5v ? 4.5 5.5 v v uvlo uvlo threshold uv = 0, v in rising/falling 4.22/4.1 v uv = 1, v in rising/falling 7/6.88 uvlo deglitch uvlo deglitch rising/falling 110 s i vin v in supply current en = gnd 250 a i vinq en = high, no load, ccm en = high, no load, psm 36 ma i vinq_lp 2.6 ma internal supply voltage v cc internal biasing supply i load = 0ma ? 4.9 5 5.1 v i vcc internal biasing supply current v in = 12v ? 10 ma v uvlo uvlo threshold for v cc v cc rising 3.8 v v cc falling 3.6 v uvlo deglitch uvlo deglitch for v cc falling edge 110 s xr 77103 rev1b
4/28 electrical characteristics (continued) t a = 25c, v in = 12v, en = v cc , f sw = 1mhz, unless otherwise specified. limits applying over the full operating temperature range are denoted by a ?. symbol parameter conditions ? min typ max units protections t sd thermal shutdown temperature temperature rising, non-latch off. t sd release threshold, temperature = t sd -hy tsd 160 c hy tsd thermal shutdown hysteresis 20 c t sd_deglitch thermal shutdown deglitch 110 s v ovbuck threshold voltage for buck overvoltage output rising (hs fet will be forced off) 109 % output falling (hs fet will be allowed to switch) 107 % buck converter f sw switching frequency i 2 c control ? 0.3 2.2 mhz v outx output voltage range ? 0.8 6 v output voltage resolution 0.05 v adjustable soft-start period range ? 0.5 4 ms i limx peak inductor current limit range ? 1 4 a i limx peak inductor current limit accuracy peak inductor current limit set at 3a ? 25 25 % r on_hsx hs switch on-resistance v in = 12v 200 m r on_ls1 ls switch on-resistance of buck1 v in = 12v 60 m r on_ls2/3 ls switch on-resistance of buck2/3 v in = 12v 80 m i o output current capability continuous loading 2 (1) a d max maximum duty cycle 95 % t on min minimum on time 120 ns line regulation (v ox /v inx ) v inx = 5.5 to 14v, i ox = 1a 0.5 %v o load regulation (v ox /i ox ) i o = 10 to 90%, i o = max 0.5 %v o /a output voltage accuracy v in = 12v ? -1 normal 1 % 5.5v v in 14v ? -2 normal 2 sync range synchronization range ? f sw + 5% 2.31 mhz sync d_min synchronization signal minimum duty cycle ? 40 % sync d_max synchronization signal maximum duty cycle ? 60 % note: 1. subject to thermal derating. design must not exceed the package thermal rating. xr 77103 rev1b
5/28 electrical characteristics (continued) t a = 25c, v in = 12v, en = v cc , f sw = 1mhz, unless otherwise specified. limits applying over the full operating temperature range are denoted by a ?. symbol parameter conditions ? min typ max units power good reset generator v uvbuck threshold voltage for buck under voltage output falling, (disabled after t on_hiccup ) 85 % output rising, (pg will be asserted) 90 t pg_deglitch deglitch time rising and falling 11 ms t on_hiccup hiccup mode on time v uvbuckx asserted 12 ms t off_hiccup hiccup mode off time once t off_hiccup elapses, all converters will start up again 15 ms t rp minimum reset period 1 s r pg power good pull-down on resistance 14 50 input threshold (sda, scl, nwr, a0) v ih input threshold high v input rising, v l = 3.3v ? 1.52 1.83 v v il input threshold low v input falling, v l = 3.3v ? 0.98 1.24 v a0, nwr pull up resistor 100 k input threshold (sync, en) v ih input threshold high v input rising ? 2.07 2.53 v v il input threshold low v input falling ? 1.36 1.67 v xr 77103 rev1b
6/28 electrical characteristics (continued) t a = 25c, v in = 12v, en = v cc , f sw = 1mhz, unless otherwise specified. limits applying over the full operating temperature range are denoted by a ?. symbol parameter conditions ? min typ max units i 2 c interface v l supply voltage 3.3 v v ol_i2c sda logic output low voltage at 3ma sink current ? 0.4 v f scl scl clock frequency ? 400 khz t high scl clock high period ? 0.6 s t low scl clock low period ? 1.3 s t sp i 2 c spike rejection filter pulse width ? 0 50 ns t su;dat i 2 c data setup time ? 100 ns t hd;dat i 2 c data hold time ? 0 900 ns t r sda, scl rise time cb = total capacitance of bus line in pf ? 20 + 0.1 x c b 300 ns t f sda, scl fall time cb = total capacitance of bus line in pf ? 20 + 0.1 x c b 300 ns t buf i 2 c bus free time between stop and start ? 1.3 s t su;sta i 2 c repeated start condition setup time ? 0.6 s t hd;sta i 2 c repeated start condition hold time ? 0.6 s t su;sto i 2 c stop condition setup time ? 0.6 s t vd;dat i 2 c data valid time ? 0.9 s t vd;ack i 2 c data valid acknowledge time ? 0.9 s c b i 2 c bus capacitive load ? 400 pf c sda sda input capacitance ? 10 pf c scl scl input capacitance ? 10 pf start condition (s) protocol scl sda bit 7 msb (a7) bit 6 (a6) bit 0 lsb (r/w) acknowledge (a) stop condition (p) t su;sta t low t high 1/f scl t buf t hd;sta t su;dat t r t hd;dat t f t sp t su;sto t vd;dat t vd;ack figure 2. i 2 c bus timing diagram xr 77103 rev1b
7/28 pin configuration pin functions pin number pin name description 1 vout3 buck 3 output sense pin. 2 comp3 compensation pin for buck 3. connect a series rc circuit to this pin for compensation. 3 a0 i 2 c address select pin. a0 is internally pulled high through a 100k? pull up resistor. 4 vin (1) ic supply pin. connect a capacitor as close as possible to this pin and agnd. 5 gnd ground. 6 vcc internal supply. connect a ceramic capacitor from this pin to agnd. vcc tied to vin for vin = 5v 7 comp1 compensation pin for buck 1. connect a series rc circuit to this pin for compensation. 8 vout1 buck 1 output sense pin. 9 bst1 bootstrap capacitor for buck 1. connect a bootstrap capacitor from this pin to lx1. 10 vin1 (1) input supply for buck 1. connect a capacitor as close as possible to this pin and pgnd. 11 lx1 switching node for buck 1. 12 lx1 switching node for buck 1. 13 lx2 switching node for buck 2. 14 lx2 switching node for buck 2. 15 vin2 (1) input supply for buck 2. connect a capacitor as close as possible to this pin and pgnd. 16 bst2 bootstrap capacitor for buck 2. connect a bootstrap capacitor from this pin to lx2. 17 vout2 buck 2 output sense pin. 18 comp2 compensation pin for buck 2. connect a series rc circuit to this pin for compensation. 19 dgnd digital ground. 20 nwr write protection input for nvm. the data can be written to nvm when this pin is low. this pin is internally pulled high through 100k? pull up resistance. note: 1. vin, vin1, vin2, and vin3 must be tied together. bst1 comp3 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 vout3 vl pgood sync gnd vout1 comp1 vin1 lx1 vin2 bst2 a0 dgnd scl sda nwr en vout2 comp2 bst3 vin3 lx3 vin agnd vin lx3 lx1 lx2 lx2 vcc xr 77103 rev1b
8/28 pin functions (continued) pin number pin name description 21 sda data i/o pin for i 2 c serial interface. 22 scl clock input pin for i 2 c serial interface. 23 vl supply pin for i 2 c interface. supply 3.3v typically for i 2 c communication. this pin can be left floating if the i 2 c interface is not used. 24 pgood power good output. open drain output asserted after all converters are sequenced and within regulation. 25 sync external clock input pin. connect to agnd when unused. 26 en enable control input. set en high to enable converters. 27 agnd analog ground. 28 vin (1) ic supply pin. connect a capacitor as close as possible to this pin and agnd. 29 lx3 switching node for buck 3. 30 lx3 switching node for buck 3. 31 vin3 (1) input supply for buck 3. connect a capacitor as close as possible to this pin and pgnd. 32 bst3 bootstrap capacitor for buck 3. connect a bootstrap capacitor from this pin to lx3. - e-pad power ground (pgnd). note: 1. vin, vin1, vin2, and vin3 must be tied together. xr 77103 rev1b
9/28 typical performance characteristics all data taken at t a = 25c unless otherwise specified. -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 0.4 0.8 1.2 1.6 2 i out (a) ?v out /v out (%) figure 3. load regulation 12v in , 3.3v out , f sw = 1mhz enable channel 3 channel 2 channel 1 figure 4. power-up sequence with delay v out ac 20mhz i out di/dt 2.5a/s 148.0mv -132.0mv figure 5. 12v in , 3.3v out , f sw = 500khz transient response, 0.5a to 1.0a v out ac 20mhz i out di/dt 2.5a/s 68.0mv -66.0mv figure 6. 5v in , 1.8v out , f sw = 500khz transient response, 0.5a to 1.0a v out ac 20mhz i out di/dt 2.5a/s 176.0mv -164.0mv figure 7. 12v in , 5.0v out , f sw = 1mhz transient response, 0.5a to 1.0a v out ac 20mhz i out di/dt 2.5a/s 132.0mv -120.0mv figure 8. 5v in , 3.3v out , f sw = 1mhz transient response, 0.5a to 1.0a xr 77103 rev1b
10/28 typical performance characteristics (continued) efficiency f sw = 500khz, t a = 25c, no airflow, only individual channel operating, inductor losses are included. i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 9. efficiency channel 1, 12v in 3.3v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 10. efficiency channel 1, 5v in 3.3v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 11. efficiency channel 2, 12v in 1.8v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 12. efficiency channel 2, 5v in 1.8v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 13. efficiency channel 3, 12v in 1.2v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 14. efficiency channel 3, 5v in 1.2v out xr 77103 rev1b
11/28 typical performance characteristics (continued) efficiency f sw = 1mhz, t a = 25c, no airflow, only individual channel operating, inductor losses are included. i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 15. efficiency channel 1, 12v in 3.3v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 16. efficiency channel 1, 5v in 3.3v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 17. efficiency channel 2, 12v in 1.8v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 18. efficiency channel 2, 5v in 1.8v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 19. efficiency channel 3, 12v in 2.5v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 20. efficiency channel 3, 5v in 1.2v out xr 77103 rev1b
12/28 typical performance characteristics (continued) thermal characteristics t ambient (c) power dissipation in package (w) 0 0.5 1 1.5 2 2.5 3 3.5 4 0 10 20 30 40 50 60 70 80 90 100 110 120 figure 21. package thermal derating i out (a) power loss (w) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 3.3v figure 22. channel 1 power loss at f sw = 500khz, v in = 12v, no airflow i out (a) power loss (w) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.4 0.8 1.2 1.6 2 0.9 1.2v 1.8v 3.3v figure 23. channel 2 power loss at f sw = 500khz, v in = 12v, no airflow i out (a) power loss (w) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.4 0.8 1.2 1.6 2 0.9 1.2v 1.8v 3.3v figure 24. channel 3 power loss at f sw = 500khz, v in = 12v, no airflow i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 3.3v figure 25. channel 1 power loss at f sw = 500khz, v in = 5v, no airflow i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 3.3v figure 26. channel 2 power loss at f sw = 500khz, v in = 5v, no airflow xr 77103 rev1b
13/28 typical performance characteristics (continued) thermal characteristics i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 3.3v figure 27. channel 3 power loss at f sw = 500khz, v in = 5v, no airflow i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.8v 2.5v 3.3v figure 28. channel 1 power loss at f sw = 1mhz, v in = 12v, no airflow i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.8v 2.5v 3.3v figure 29. channel 2 power loss at f sw = 1mhz, v in = 12v, no airflow i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.8v 2.5v 3.3v figure 30. channel 3 power loss at f sw = 1mhz, v in = 12v, no airflow i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 2.5v 3.3v figure 31. channel 1 power loss at f sw = 1mhz, v in = 5v, no airflow i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 2.5v 3.3v figure 32. channel 2 power loss at f sw = 1mhz, v in = 5v, no airflow xr 77103 rev1b
14/28 typical performance characteristics (continued) thermal characteristics functional block diagram xr77103 25 26 osc pgood internal supply 31 15 10 6 24 27 19 5 ep vin3 vin2 vin1 vcc pgood gnd dgnd agnd en sync buck1 9 12 11 8 7 buck2 16 14 13 17 18 buck3 32 30 29 1 2 comp3 vout3 lx3 bst3 28 4 vin vin lx3 comp1 vout1 lx1 bst1 lx1 comp2 vout2 lx2 bst2 lx2 i 2 c interface 22 scl 21 sda nvm 23 vl 20 nwr a0 3 figure 34. functional block diagram i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 2.5v 3.3v figure 33. channel 3 power loss at f sw = 1mhz, v in = 5v, no airflow xr 77103 rev1b
15/28 applications information operation xr77103 is a power management ic with three step-down buck converters. both high-side and low-side mosfets are integrated to provide fully synchronous conversion with higher efficiency. xr77103 can support 4.5v to 14v input supply, high load current, 300khz to 2.2mhz clocking. the buck converters have an optional psm mode which can improve power dissipation at light loads. alternatively, the device implements a constant frequency mode. the wide switching frequency of 300khz to 2.2mhz allows for efficiency and size optimization. the switching frequency is adjustable by writing data through i 2 c. the sync pin also provides means to synchronize the power converter to an external clock signal. input ripple is reduced by 180 degree out-of-phase operation among converters. all three buck converters have peak current mode control which simplifies external frequency compensation. each buck converter has an individual peak inductor current limit which is set through i 2 c. the adjustable current limit enables high efficiency design with smaller and less expensive inductors. the device has a power good comparator monitoring the output voltages. each converter has its own soft-start independently controlled through i 2 c. continuous conduction mode (ccm) this is a natural mode of a synchronous buck converter. advantage of the ccm mode is that the switching frequency is always constant and allows for better emi control in the system. the downside of ccm mode is that at light loads system efficiency will become lower. pulse skipping mode (psm) in order to improve efficiency at light load the device implements two functions. both functions are enabled simultaneously. one function is a zero current detect comparator (zcd) which detects zero current in the inductor and turns off synchronous mosfet, preventing negative inductor current. this ensures that the device enters dcm mode as the load decreases. in this mode the device still operates at a constant frequency. the second function is an internal skip comparator. this comparator detects low level of output current. if this low level is detected the device will start to skip pulses. this is done to improve light load efficiency by effectively reducing switching frequency. for details contact powertechsupport@exar.com. output voltage setting output voltage of each converter can be programmed by i 2 c interface. it can be set from 0.8v to 6v with 6-bit resolution. the registers 00h to 02h are allocated to setting each output of the converters. alternatively, output voltages can be set externally using external resistor dividers. setting extx (bit 7) of the registers 00h to 02h allows external resistor divider for feedback. output voltage is determined by the following equation. v ox v 1 r1 r r 1 1 r1 r2 xr77103 v ox xr77103 v ox figure 35. output voltage setting this feature can make the device applicable to avs (automatic voltage scaling) system. output voltage can be adjusted automatically by external dc voltage. figure 36 shows application circuit of supply for avs system. xr77103 soc v outx v ox r1 r dac avs supply pvt mnt v dac r2 figure 36. avs control xr 77103 rev1b
16/28 applications information (continued) frequency compensation in order to properly frequency compensate the device, the following component selection is recommended. the table below is for 2a loads. v in (v) v out (v) l (h) c out (f) r comp (k?) c comp (nf) 500khz switching frequency 12/5.0 1.0 2.2 22 x 3 10 4.7 12/5.0 1.2 2.2 22 x 3 10 4.7 12/5.0 1.5 3.3 22 x 3 20 4.7 12/5.0 1.8 3.3 22 x 2 20 4.7 12/5.0 2.5 4.7 22 x 2 20 4.7 12/5.0 3.3 4.7 22 x 1 20 4.7 12 5.0 6.8 22 x 1 20 4.7 1mhz switching frequency 5.0 1.0 1.5 22 x 3 10 4.7 5.0 1.2 1.5 22 x 3 10 4.7 5.0 1.5 1.5 22 x 2 20 4.7 12/5.0 1.8 1.5 22 x 2 20 4.7 12/5.0 2.5 3.3 22 x 1 20 4.7 12/5.0 3.3 3.3 22 x 1 20 4.7 12 5.0 3.3 22 x 1 20 4.7 for configurations not listed above contact powertechsupport@exar.com. switching frequency setting switching frequency can be set from 300khz to 2.2mhz with a 100khz step. lower 5 bits of the register 09h are allocated to setting the switching frequency. current limit setting peak inductor current limit level of each converter can be set individually from 1a to 4a with a 0.5a step. lower 3 bits of the registers 06h, 07h and 08h are allocated to setting the peak inductor current limit of buck 1, buck 2 and buck 3 respectively. soft-start time setting soft-start time of each converter can be set individually (see figure 36). lower 3 bits of the registers 03h, 04h and 05h are allocated to setting the soft-start time of buck 1, buck 2 and buck 3 respectively. the soft-start times are relative to switching frequency. they scale with switching frequency. at switching frequency set at 1mhz, the available soft-start range is from 0.5ms to 4ms with a 0.5ms step. at switching frequency set at 500khz, the available soft-start range is from 1ms to 8ms with a 1ms step. en vout1 vout2 vout3 t dly1 vout1 t ss3 t dly2 t ss2 t dly3 t ss3 figure 37. programmable soft-start time and delay time of each converter delayed start-up all outputs start up once en pin is high and select bits of each converter are set. if a delayed start-up is required on any of the buck converters, set delay time of each converter. the bits [6:4] of the registers 03h, 04h and 05h are allocated to setting delay time of buck 1, buck 2 and buck 3 respectively. the soft-start delay times are relative to switching frequency. they scale with switching frequency. at switching frequency set at 1mhz, the available soft-start delay time range is from 0ms to 35ms with a 5ms step. at switching frequency set at 500khz, the available soft-start delay time range is from 0ms to 70ms with a 10ms step. xr 77103 rev1b
17/28 applications information (continued) synchronization the status of the sync pin will be ignored during start-up and the xr77103s control will only synchronize to an external signal after the pgood signal is asserted. when synchronization is applied, the pwm oscillator frequency must be lower than the sync pulse frequency to allow the external signal trumping the oscillator pulse reliably. when synchronization is not applied, the sync pin should be connected to agnd. although the device can lock to external clock running up to 2.31mhz, doing this will alter the start-up times, start-up delays and pgood delays, and there will be higher losses than what is shown in figures 22-33. for details contact powertechsupport@exar.com. out-of-phase operation all converters operate in phase, or one converter operates 180 degrees out-of-phase with the other two converters (see figure 38). the phase shift among the converter is programmable. the bits 6, 5 of the register 09h are allocated for this feature. this enables the system, having less input ripple, to lower component cost, save board space and reduce emi. lx1 lx2 lx3 lx1 lx2 lx3 lx1 lx2 lx3 lx1 lx2 lx3 all converters in phase buck1 and buck2/3 are 180 out-of-phase buck3 and buck1/2 are 180 out-of-phase buck2 and buck1/3 are 180 out-of-phase figure 38. out-of-phase operation two buck regulators in parallel operation (current sharing) the xr77103 can be used in parallel operation to increase output current capacity. figure 39 shows one of possible configurations. to enable this a user needs: hardware configuration a) to connect both v outx together. b) to connect both c ompx together. software configuration a) to set 180 out-of-phase operation between buck regulators (register 09h). b) programming both v outx to the same output. then, two out of three bucks will run in parallel and load current is shared in average. the ideal case is to use buck 2 and buck 3 in parallel operation since they are both identical in design. buck2 comp2 vout2 lx2 lx2 vout3 lx3 lx3 comp3 buck3 v out figure 39. parallel operation xr 77103 rev1b
18/28 applications information (continued) power good the pgood pin is an open drain output. the pgood pin is pulled low when any buck converter is pulled below 85% of the nominal output voltage. the pgood is pulled up when selected buck converters outputs are more than 90% of their nominal output voltage and the pgood reset timer expires. the polarity of the pgood is active high. the pgood reset time is determined by following equation. figure 40 shows the relationship between switching frequency and the pgood reset time. for example, when the switching frequency is 1mhz, the pgood reset time is 1s. v ox v 1 r1 r r 1 1 switching frequency (mhz) pgood reset time(s) 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 0.5 1.0 1.5 2.0 figure 40. pgood reset time vs. f sw selectable uvlo threshold the threshold for uvlo is selectable (7v/4.2v). when input voltage is higher, 9v and 12v for example, both settings can be used. however, when the input voltage is 5v, the uvlo setting must be 4.2v. supply voltage for data programming and writing to nvm v l is the supply voltage for i 2 c interface and is required for all i 2 c transactions. the v l pin can be left floating if the i 2 c interface is not used. to write data to nvm, v in must be 8v or higher. the state of the nwr pin determines where the data gets written to. if the nwr pin is pulled low to ground, the data is written to the nvm. the i 2 c write transaction can start immediately after the nwr pin has been pulled low. a 100ms delay shall be added in between consecutive i 2 c writes to the nvm. after each byte is written to nvm location, the data gets automatically transferred to the run time equivalent register. if the nwr pin is pulled high or left floating, the data gets written to run time registers. in case v in is below 8v, writing to nvm is not possible in which case the nwr pin must be pulled high or left floating to assure reliable writing to run time registers. v l v in en nwr i 2 c write behavior 3.3v 8v low low write to nvm, values loaded to run-time registers 3.3v 8v high low not supported 3.3v 8v x low write has no effect 3.3v 4.5v to 14v low high write to run-time registers with offsets > 02h 3.3v 4.5v to 14v high high not supported 3.3v 4.5v to 14v x high write to run-time registers with offsets 02h in addition, the nwr pin state determines where data gets read from in case a read i 2 c command is transmitted on the bus. when initiating read transaction while the nwr pin is pulled high or left floating, the data is read from the run time registers. reading run time registers can be done at any time. on the other hand if the nwr pin is pulled low at the time when a read transaction is sent, the data is read from nvm. it is recommended not to permanently pull the nwr pin low. in designs where the nwr pin is pulled low permanently, the host shall not initiate read transaction while channels are enabled. failing to do so will cause regulation interruption. reading in this scenario shall be done while en is low and channels are shut down. v l v in en nwr i 2 c read behavior 3.3v 4.5v to 14v low low read from nvm (when all channels are disabled) 3.3v 4.5v to 14v high low not supported 3.3v 4.5v to 14v x high read from run-time registers at power-on, the run-time registers are loaded with their default values from the nvm. this process takes approximately 200s. no i 2 c operation should be performed during this time. xr 77103 rev1b
19/28 applications information (continued) thermal design proper thermal design is critical in controlling device temperatures and in achieving robust designs. there are a number of factors that affect the thermal performance. one key factor is the temperature rise of the devices in the package, which is a function of the thermal resistances of the devices inside the package and the power being dissipated. the thermal resistance of the xr77103 (30c/w) is specified in the operating conditions section of this datasheet. the ja thermal resistance specification is based on the xr77103 evaluation board operating without forced airflow. since the actual board design in the final application will be different, the thermal resistances in the final design may be different from those specified. the package thermal derating and power loss curves are shown in figures 21 through 33. these correspond to input voltages of 12v and 5v, and 500khz and 1mhz switching frequencies. layout guidelines proper pcb layout is crucial in order to obtain a good thermal and electrical performance. for thermal considerations it is essential to use a number of thermal vias to connect the central thermal pad to the ground layer(s). in order to achieve good electrical and noise performance following steps are recommended: q place the output inductor close to the lx pins and minimize the area of the connection. doing this on the same layer is advisable. q central thermal pad, pgnd, shall be connected as many layers as possible for good thermal performance. the input capacitors connected between vin1, vin2, vin3 and pgnd represent an ac current loop which should be minimized. pgnd should connect to the system ground with vias placed at the output filtering capacitors q the ac current loop created by the output inductors, output filtering capacitors, and the regulator pins should also be minimized. however this loop is less critical than the input capacitors. q gnd, agnd, dgnd can all be connected at the device and be connected to system ground at the output capacitor. q compensation networks shall be placed close to the pins and referenced to agnd. q vcc bypass capacitor shall be placed close to the pin and connected to agnd. i2c bus interface the xr77103 features an i 2 c compatible, 2-wire serial interface consisting of a serial-data line (sda) and a serial clock line (scl). sda and scl facilitate communication between the ic and the master device at clock rates up to 400khz. the i 2 c interface follows all standard i 2 c protocols. some information is provided below. for additional information, refer to the i 2 c-bus specifications. sda scl s start condition p stop condition figure 41. i 2 c start and stop conditions start condition the master initiates data transfer by generating a start condition. the start condition is when a high-to-low transition occurs on the sda line while scl is high, as shown in figure 41. slave address cycle after the start condition, the first byte sent by the master is the 7-bit address and the read/write direction bit r/w on the sda line. if the address matches the xr77103s internal fixed i 2 c slave address, the xr77103 will respond with an acknowledge by pulling the sda line low for one clock cycle while scl is high. data cycle after the master detects this acknowledge, the next byte transmitted by the master is the sub-address. this 8-bit sub-address contains the address of the register to access. the xr77103 register map is on page 20. xr 77103 rev1b
20/28 applications information (continued) stop condition to signal the end of the data transfer, the master generates a stop condition by pulling the sda line from low to high while the scl line is high, as shown in figure 41. figures 42 and 43 illustrate a write and a read cycle. for complete details, see the i 2 c-bus specifications. s slave address w a register address a data a p notes: white block = host to xr77103, orange block = xr77103 to host. figure 42. master writes to slave s slave address w a register address a s slave address r a data na p notes: white block = host to xr77103, orange block = xr77103 to host. figure 43. master reads from slave slave address the slave address is one byte of data which is used as the unique identifier. the first 7 bits of the slave address are hard- coded and the least significant bit (lsb) of the slave address byte is the read/write (r/w) bit which is used to determine whether a command is a write command or a read command. the slave address is the first byte of information sent to the device after the start condition. table below shows the possible slave addresses for the xr77103. device address (a0 = low) address (a0 = high) xr77103 0x74 0x75 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 1 1 0 1 0 a0 r/w register map register address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 factory default nvm value 00h v buck1 ext1 v buck1 [6:0] v buck2 [6:0] v buck3 [6:0] 00h 01h v buck2 ext2 02h v buck3 ext3 03h soft-start and delay 1 - dly1 [2:0] - sst1 [2:0] 15h 04h soft-start and delay 2 - dly2 [2:0] - sst2 [2:0] 05h soft-start and delay 3 - dly3 [2:0] - sst3 [2:0] 06h current limit 1 - - - - - lim1 [2:0] 05h 07h current limit 2 - - - - - lim2 [2:0] 08h current limit 3 - - - - - lim3 [2:0] 09h switching frequency and phase - phs [1:0] - frq [4:0] - - - - 42h 0ah pwr - uv - - psm buck3 buck2 buck1 7fh xr 77103 rev1b
21/28 applications information (continued) v buck1 register (00h) the v buck1 register has 7 bits of data for setting output of buck 1 and 1 bit of data for use of external feedback voltage through a resistor divider. the buck 1 programmable voltage range is from 0.8v to 6v with 0.05v resolution. when ext1 is set to 1, the output voltage is adjusted by the external resistor divider from the output to ground with the center tap connected to v out1 pin regardless of the value of the output voltage setting register. the factory default nvm value is 00h (0.8v). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext1 d6 d5 d4 d3 d2 d1 d0 hex v out (v) hex v out (v) 00 0.8 1a 2.1 01 0.85 1b 2.15 02 0.9 1c 2.2 03 0.95 1d 2.25 04 1 1e 2.3 05 1.05 20 2.4 06 1.1 21 2.45 07 1.15 22 2.5 08 1.2 23 2.55 09 1.25 24 2.6 0a 1.3 25 2.65 0b 1.35 26 2.7 0c 1.4 27 2.75 0d 1.45 28 2.8 0e 1.5 29 2.85 10 1.6 2a 2.9 11 1.65 2b 2.95 12 1.7 2c 3 13 1.75 2d 3.05 14 1.8 2e 3.1 15 1.85 30 3.2 16 1.9 31 3.25 17 1.95 32 3.3 18 2 33 3.35 19 2.05 34 3.4 hex v out (v) hex v out (v) 35 3.45 50 4.8 36 3.5 51 4.85 37 3.55 52 4.9 38 3.6 53 4.95 39 3.65 54 5 3a 3.7 55 5.05 3b 3.75 56 5.1 3c 3.8 57 5.15 3d 3.85 58 5.2 3e 3.9 59 5.25 40 4 5a 5.3 41 4.05 5b 5.35 42 4.1 5c 5.4 43 4.15 5d 5.45 44 4.2 5e 5.5 45 4.25 60 5.6 46 4.3 61 5.65 47 4.35 62 5.7 48 4.4 63 5.75 49 4.45 64 5.8 4a 4.5 65 5.85 4b 4.55 66 5.9 4c 4.6 67 5.95 4d 4.65 68 6 4e 4.7 xr 77103 rev1b
22/28 applications information (continued) v buck2 register (01h) the v buck2 register has 7 bits of data for setting output of buck 2 and 1 bit of data for use of external feedback voltage through a resistor divider. the buck 2 programmable voltage range is from 0.8v to 6v with 0.05v resolution. when ext2 is set to 1, the output voltage is adjusted by the external resistor divider from the output to ground with the center tap connected to v out2 pin regardless of the value of the output voltage setting register. the factory default nvm value is 00h (0.8v). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext2 d6 d5 d4 d3 d2 d1 d0 v buck3 register (02h) the v buck3 register has 7 bits of data for setting output of buck 3 and 1 bit of data for use of external feedback voltage through a resistor divider. the buck 3 programmable voltage range is from 0.8v to 6v with 0.05v resolution. when ext3 is set to 1, the output voltage is adjusted by the external resistor divider from the output to ground with the center tap connected to v out3 pin regardless of the value of the output voltage setting register. the factory default nvm value is 00h (0.8v). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext3 d6 d5 d4 d3 d2 d1 d0 sst1 and dly1 register (03h) soft-start time 1 and delay time 1 register has 6 effective bits. three bits are for setting soft-start time of buck 1 and three bits are for setting delay time from en to buck 1 start-up. the factory default soft-start and delay times are 6ms and 10ms respectively at 500khz switching frequency. both soft-start and delay times are relative to the switching frequency. they will be two times smaller at 1mhz switching frequency. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x d6 d5 d4 x d2 d1 d0 d2 d1 d0 t ss (ms) at f sw = 500khz t ss (ms) at f sw = 1mhz 0 0 0 1 0.5 0 0 1 2 1 0 1 0 3 1.5 0 1 1 4 2 1 0 0 5 2.5 1 0 1 6 3 1 1 0 7 3.5 1 1 1 8 4 d6 d5 d4 t dly (ms) at f sw = 500khz t dly (ms) at f sw = 1mhz 0 0 0 0 0 0 0 1 10 5 0 1 0 20 10 0 1 1 30 15 1 0 0 40 20 1 0 1 50 25 1 1 0 60 30 1 1 1 70 35 xr 77103 rev1b
23/28 applications information (continued) sst2 and dly2 register (04h) soft-start time 2 and delay time 2 register has 6 effective bits. three bits are for setting soft-start time of buck 2 and three bits are for setting delay time from en to buck 2 start-up. the factory default soft-start and delay times are 6ms and 10ms respectively at 500khz switching frequency. both soft-start and delay times are relative to the switching frequency. they will be two times smaller at 1mhz switching frequency. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x d6 d5 d4 x d2 d1 d0 sst3 and dly3 register (05h) soft-start time 3 and delay time 3 register has 6 effective bits. three bits are for setting soft-start time of buck 3 and three bits are for setting delay time from en to buck 3 start-up. the factory default soft-start and delay times are 6ms and 10ms respectively at 500khz switching frequency. both soft-start and delay times are relative to the switching frequency. they will be two times smaller at 1mhz switching frequency. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x d6 d5 d4 x d2 d1 d0 current limit 1 register (06h) current limit 1 register has 3 effective bits. the factory default value is 3.5a (05h). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x x d2 d1 d0 d2 d1 d0 i lim1 (a) 0 0 0 1 0 0 1 1.5 0 1 0 2 0 1 1 2.5 1 0 0 3 1 0 1 3.5 1 1 0 4 current limit 2 register (07h) current limit 2 register has 3 effective bits. the factory default value is 3.5a (05h). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x x d2 d1 d0 current limit 3 register (08h) current limit 3 register has 3 effective bits. the factory default value is 3.5a (05h). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x x d2 d1 d0 xr 77103 rev1b
24/28 applications information (continued) switching frequency and phase register (09h) switching frequency and phase register has 7 effective bits. the 5 least significant bits are setting switching frequency. the factory default value is 500khz (00010b). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x d6 d5 d4 d3 d2 d1 d0 d [4:0] hex f sw [mhz] d [4:0] hex f sw [mhz] 00 0.3 0a 1.3 01 0.4 0b 1.4 02 0.5 0c 1.5 03 0.6 0d 1.6 04 0.7 0e 1.7 05 0.8 0f 1.8 06 0.9 10 1.9 07 1 11 2 08 1.1 12 2.1 09 1.2 13 2.2 the bits 5 and 6 are for setting phase shift among buck converters. the factory default value is channel 3 180 out-of-phase in respect to the channels 1 and 2 (10b). d6 d5 phase shift 0 0 all converters operate in phase 0 1 buck1 and buck2/3 operate 180 out-of-phase 1 0 buck1/2 and buck3 operate 180 out-of-phase 1 1 buck1/3 and buck2 operate 180 out-of-phase pwr register (0ah) pwr register has 5 effective bits. the bits 0-2 select which channels will be enabled at transition of enable pin from low to high. the state of the bit 3 determines whether buck converters operate in pulse skipping mode or not. setting this bit to 1 allows pulse skipping mode operation to minimize power losses at light load levels. the bit 6 determines threshold voltage for v in uvlo. the factory default of this register is 7fh. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x uv x x psm buck 3 buck 2 buck 1 0 1 d0 buck 1 not used select d1 buck 2 not used select d2 buck 3 not used select d3 psm disable enable d6 uv 4.2v 7v xr 77103 rev1b
25/28 applications information (continued) typical applications cbst_ch1 47nf l out _ch1 v in1 v out1 c out _ch1 c in _ch1 v in1 l out _ch2 v in2 v out2 c out _ch2 c in _ch2 v in2 xr77103 vout3 1 comp3 2 a0 3 vin 4 gnd 5 vcc 6 comp1 7 vout1 8 bst1 9 vin1 10 lx1 11 lx1 12 lx2 13 lx2 14 vin2 15 bst2 16 pgood 24 23 22 21 20 dgnd 19 comp2 18 vout2 17 bst3 32 vin3 31 lx3 30 lx3 29 vin 28 agnd 27 en 26 sync 25 e-pad 33 vl scl sda nwr vout2 vout1 vout3 pg rpg v cc cp_ch2 rc_ch2 cc_ch2 cp_ch1 rc_ch1 cc_ch1 v cc v in c vcc cp_ch3 rc_ch3 cc_ch3 l out _ch3 v out3 c out _ch3 v in cbst_ch3 47nf c in _ch3 v in3 v in3 c2_in v in rgnd sync en c1_in vl scl sda nwr a0 cbst_ch2 47nf figure 44. typical applications schematic xr 77103 rev1b
26/28 package description 1. all dimensioins are in millimeters 2. dimensions and tolerance per jedec mo-220 top view side view bottom view xr 77103 rev1b
27/28 package description (continued) recommended land pattern xr 77103 rev1b
www.exar.com 28/28 tel.: +1 (510) 668-7000 fax: +1 (510) 668-7001 email: powertechsupport@exar.com order information part number operating temperature range environmental rating package packaging quantity marking xr77103elb -40c t j 125c rohs compliant, halogen free 32-pin, 4mm x 4mm tqfn package bulk exar xr77103 yywwf00 xxxxxxx xr77103elbtr 3k/tape and reel XR77103EVB-DEMO-1 xr77103 evaluation board XR77103EVB-DEMO-1-kit xr77103 evaluation board with interface board and software note: yy = year, ww = work week, xxxxxx = lot number. revision history revision date description 1a march 2016 initial release 1b may 2016 clarified pin descriptions. added description for continuous conduction mode and pulse skipping mode. added i 2 c bus timing waveform and updated i 2 c symbols and functional description. added details for nvm programming and behavior. added factory default nvm value to register map table. updated application circuit. updated layout guidelines. exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation conveys no license under any patent or other right and makes no representation that the circuits are free of patent infringement. while the information in this publication has been carefully checked, no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. exar, xr and the xr logo are registered trademarks of exar corporation. all other trademarks are the property of their respective owners. ?2016 exar corporation xr77103_ds_052616 xr 77103 rev1b 48760 kato road fremont, ca 94538 usa

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